Meeting Your Peers Engineers #4 – NXP Semiconductors: High thermal die attach materials: their performance and reliability in semiconductor packages 18 March 2025

Location/Address
Address
Noviotech Campus
6534 AT
Nijmegen
About this event

Date: March 18th, 2025
Time: 12:00 – 13:45 (Lunch included)
Location: Noviotech Campus, Building M, Meet&Greet

We invite you to the 4th edition of Meeting Your Peers for Engineers! All engineers from semiconductor companies in the region are welcome to this lunch event.

This time, NXP will share insights into their company, including their latest innovations in semiconductor technology, with a focus on thermal die attach materials and their performance and reliability in semiconductor packages.

The Die Attach consortium has been working since 2009 on the replacement of Pb-containing solder as die attach and clip attach material in semiconductor packages. The DA5 member companies work closely with die attach material suppliers to tackle technical challenges such as delamination, thermal management and issues related to the die attach process. More information can be found here.

Following that, Henri Antony Martin, researcher at CITC, will give a presentation about ‘Co-Packaged Electronics with Microfluidics for Direct-to-Package Cooling’.

High-power semiconductor devices experiencing heightened temperature swings rely on active cooling technologies to extend their operating ranges. However, the actively cooled heat sinks are bulky and require substantial coolant volumes with limitations in cooling efficiency. Integrating microchannels directly onto semiconductor substrates for direct-to-chip cooling minimizes the distance between thermal junctions and cooling elements, critical for improving thermal dissipation efficiencies. However, chip-level integration requires complex fabrication steps on active semiconductor substrates at a wafer level, bringing major costs and processing challenges. We propose embedding microchannels at a package level, i.e., within the electronic package substrate, thereby combining the advantages of direct-to-chip cooling by utilizing traditional backend package assembly processes.

 

Program

12:00 – 12:30  Walk in & Lunch

12:30 – 12:40  Presentation: Semiconductor Package Development at NXP  by Pascal  Oberndorff (Sr. Director, NXP Semiconductors)

12:40 – 13:40

In-depth presentation:

  • Die Attach 5 consortium (Andrei Damian, Package Development engineer, NXP)

  • Co-Packaged Electronics with Microfluidics for Direct-to-Package Cooling (Henry Antony Martin, Researcher, CITC)

13:40 –13:45  Wrap-up & End

 

Lunch will be provided, courtesy of NXP, the event's lunch sponsor.

 

Register
Seize the opportunity to network and expand your knowledge! Reserve your spot for this inspiring session on March 18th.

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